Re: Open pins on Alpha Clock Five

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Windell Oskay
LED D2 is controlled by pin PD6/OC2B.  LED D1 is controlled by pin PD7/OC2A.

The definitions and functions of TCCR2A and TCCR2B are given in the ATmega644’s datasheet.  

The default code to configure those two registers is as folows: 

 TCCR2A = (_BV(WGM20) | _BV(COM2B1)); // PWM, phase correct, top: FF, overflow at bottom 
 // Drive output OC2B (nightlight) with value OCR2B 

 TCCR2B = (_BV(CS20)); // System clock w/o prescaler.
// so overflow happens at 16 MHz/2*256 = 31.250 kHz
I would suggest *not* changing the clock source bits of TCCR2B, as those select the clock source used by the PWM subsystem, not which outputs are enabled.
If you do look at the datasheet, it will tell you what the different bits actually do.
In TCCR2A, the enabled bits are WGM20 and COM2B1.   
* WGM20 being enabled (Without WGM21 or WGM22) sets the mode of the timer to “Phase correct PWM.”   You don’t need to change that.   
* COM2B1 (without COM2B0) is a command to set Clear OC2B on Compare Match when up-counting, and set OC2B on Compare Match when down-counting.  This is what actually hooks the timer to the output pin. 
For a proper analogy, we should set OC2A to behave the same way, by enabling bit COM2A1, as follows: 
TCCR2A = (_BV(WGM20) | _BV(COM2B1) | _BV (COM2A1)); 
Why don’t you give that a try, and see how it does.